This invention relates to programmable logic array integrated circuit devices (“programmable logic devices” or “PLDs”), and more particularly to interconnection resources for use on programmable logic devices that increase the speed at which those devices can be made to operate. The invention also relates to such other features of PLDs as secondary signal (e.g., clock and clear signal) distribution, input/output circuitry, and cascade connections between logic modules.
Programmable-logic devices typically include (1) many regions of programmable logic, and (2) programmable interconnection resources for selectively conveying signals to, from, and/or between those logic regions. Each logic region is programmable to perform any of several different, relatively simple logic functions. The interconnection resources are programmable to allow the logic regions to work together to perform much more complex logic functions than can be performed by any individual logic region. Examples of known PLDs are shown in Wahlstrom U.S. Pat. No. 3,473,160, Freeman U.S. Pat. No. Re. 34,363, Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, and Jefferson et al. U.S. patent application Ser. No. 09/266,235, all of which are hereby incorporated by reference herein in their entireties.
A typical measure of the maximum speed at which a PLD can be made to operate is the longest time required for a signal to propagate through the device from the register of any logic region (or other resource with a register) to the register of any other logic region (or other resource with a register). A PLD cannot be safely clocked at a clock rate having a period less than this longest signal propagation time. An important design objective for most PLDs is to minimize the longest signal propagation time. Thus both the logic regions and the interconnection resources are typically designed to be time-efficient in this respect. Once this has been done, however, for a given integrated circuit fabrication technology, it is difficult to significantly further reduce the longest signal propagation time. For example, to increase the speed of interconnection resources, bigger drivers and pass transistors can be used, but the corresponding diffusion loading on the routing channels will also increase. Wider metal tracks can be used for interconnection conductors to reduce metal RC delay, but this will increase die size substantially. As a result, the final speed-up is diminished.
In view of the foregoing, it is an object of this invention to provide improved programmable logic devices.
It is a more particular object of this invention to provide improved interconnection resources for programmable logic devices.
It is a still more particular object of this invention to provide interconnection resources for programmable logic devices which reduce the longest signal propagation time characteristic of the device without the disadvantages associated with simply increasing the speed of all of those resources.
It is yet another object of this invention to improve PLDs with respect to such features as secondary (e.g., clock and clear) signal distribution, input/output circuitry, and circuitry for cascading two or more logic modules together.